Semiconductor light-emitting devices including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes (VCSELs), and edge emitting lasers are among the most efficient light sources currently available. Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials. Typically, III-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, III-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. The stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p-type regions.
FIG. 1 illustrates a device described in U.S. Pat. No. 7,348,212. FIG. 1 illustrates a flip chip light emitting device attached to a mount. The flip chip device includes a substrate 73 attached to semiconductor device layers 74, which layers include at least one light emitting or active layer disposed between an n-type region and a p-type region. N-type contact 71 and p-type contact 72 are electrically connected to the n- and p-type regions of semiconductor structure 74. Semiconductor structure 74 is connected to mount 70 via contacts 71 and 72. A metal-to-metal interconnect to connect semiconductor structure 74 to mount 70 is formed by first forming thin metal layers 76b and 77b on mount 70 and thin metal layers 76a and 77a on contacts 71 and 72, then lithographically patterning the thin metal layers into the desired arrangement, resulting in thin metal regions in the desired shape. After patterning thin metal regions 76a, 77a, 76b, and 77b, thick ductile metal layers 78 and 79 are plated on either mount 70 or contacts 71 and 72, thus on either regions 76a and 77a or regions 76b and 77b. Metal layers 78 and 79 are selected to be ductile, have high thermal and electrical conductivity, and be reasonably resistant to oxidation. The semiconductor device is then positioned on mount 70 and the device and the mount are joined by any process that results in interdiffusion between thin metal layers 76a, 77a, 76b, and 77b and thick metal layers 78 and 79. Examples of suitable processes include thermosonic bonding and thermal compression bonding, where the device and mount are heated, for example to a temperature between 150 and 600° C., often 300 to 600° C., and pressed together, for example at a pressure between 10 and 200 N/mm2 of interconnect area.